The present disclosure relates to semiconductor elements and fabrication methods for semiconductor elements, and, more particularly, to semiconductor elements capable of being utilized in a variety of different packaging methods and methods of fabricating the same.
Conventional methods of packaging semiconductor elements include mounting a semiconductor element on a mounting substrate in a face-down manner (i.e., such that a surface including electrodes is towards to the mounting substrate) as well as mounting a semiconductor such that the electrode surface is not towards to the mounting substrate.
An example of the former packaging method includes a flip-chip packaging method where bumps are formed in the electrodes of a semiconductor element. The electrodes of the semiconductor element are directly connected to the electrodes of a mounting substrate. Another example is a chip scale package (“CSP”) packaging method, where posts electrically connected to the electrodes of a semiconductor element are formed covering an element surface of the semiconductor element, a sealing resin is applied while leaving the posts exposed, and solder balls or the like are formed on the posts, so that the posts are connected to the electrodes of a mounting substrate.
An example of the latter packaging method includes a lead frame packaging method in which a semiconductor element is mounted on a lead frame so that a surface opposite an electrode surface is towards to the lead frame, the electrodes of the semiconductor element are electrically connected to lead terminals of the lead frame using wire bonding, and a sealing resin is formed to cover the entire surface of the semiconductor element mounted on the lead frame. Another example includes a chip on board (“COB”) packaging method where a semiconductor element is mounted on a mounting substrate so that a surface opposite an electrode surface is towards the mounting substrate, and the electrodes of the semiconductor element and the electrodes of the mounting substrate are electrically connected by means of wire bonding or by forming a wiring layer.
In ball grid array (“BGA”) packaging where a semiconductor element is mounted on an interposer so that the electrodes of the semiconductor element are electrically connected to solder balls (or the like) arranged on a mounting surface of the interposer, the semiconductor element may be applied using either the former or the later packaging method. In addition, in the lead frame packaging method, the semiconductor element may be connected to the lead terminal by means of a flip-chip connection.
Although there are a variety of types of packaging methods, an appropriate packaging method is selected depending on a function, a purpose of use, or the like of the semiconductor element, and a position or the like of the terminals is appropriately designed in accordance with the number or the position of the electrodes of the mounting substrate.
In addition, Japanese Laid-Open Patent Application No. 2003-174118 discloses a technique that enables changing the position of a pad in a simple manner, even after the position of the pad has been designed in a water-level chip scale package (“WLCSP”).
Semiconductor elements including a circuit for measuring temperature or time, a sensor such as a speed sensor, an acceleration sensor or a pressure sensor, or the like are used for a variety of purposes, and even semiconductor elements having the same function may utilize a variety of packaging methods.
However, in the above-described conventional techniques, the semiconductor element is usually designed to be used with only one packaging method, and the semiconductor element typically needs to be redesigned to be used with another packaging method, resulting in an increase in time or cost.
Moreover, in the technique disclosed in Japanese Laid-Open Patent Application No. 2003-174118, the pad position may changed for only one packaging method but cannot be changed for another packaging method.